In recent years, various kinds of wafers used in the manufacture of semiconductors, MEMS and the like have tend become thinner, with thicknesses between tens of micrometers to 1 mm, due to the increased density and the reduced thickness of circuit elements. A wafer is cut out from an ingot. Then the bevel part or edge part of the wafer is chamfered. The main face of the wafer is polished to a mirror-finish face. However, due to the reduced thickness of wafers, minute chipping or wafer cracking due to such chipping has become more likely to occur. For improving yield in manufacture of semiconductors and the like, a machined state of the wafer periphery has become important.
Heretofore, a chamfering method for wafers was provided as suitable for high integration of semiconductor integrated circuits (JP-A-H10-100050: patent document 1). The method involves pressing a cylindrical or columnar grindstone against the chamfering portion of the wafer consisting of an orientation flat (hereinafter, when appropriate, referred to as the OF), an outer periphery and a corner, by a predetermined pressing force while rotating the grindstone and the wafer relative to each other; soft-grinding the OF, the outer periphery and the corner, respectively, while changing the rotation speed of the wafer depending on whether the part subjected to the soft-grinding is the OF, the outer periphery or the corner; and then polishing the OF, the outer periphery and the corner, respectively, so as to perform uniform soft-grinding over the entire chamfering portion.
And heretofore, a method and an apparatus for polishing a notch and a bevel of a semiconductor wafer by use of a polishing tape was provided (JP-A-2006-303112: patent document 2).